Transistors used for integrated circuits require minimal parasitic capacitance to maximize the circuit speed and frequency. Each transistor typically includes a source region and a drain region interconnected by a channel and a gate that regulates electron flow through the channel. To minimize parasitic capacitance, traditional silicon metal-oxide semiconductor field effect transistors (MOSFETs) can employ self-aligned gate structures. Specifically, with these structures, the gate is self aligned to the channel and to the source and drain regions. Accordingly, with this configuration, the amount by which the gate overlaps the source and drain regions is at best minimal. By minimizing or eliminating the overlap between the gate and the source and drain regions, the parasitic capacitance between the gate and the source/drain is reduced.
There is currently much interest in the use of carbon-based materials, such as graphene and carbon nanotubes, as a transistor channel material. One challenge for implementation of such carbon-based devices, however, is that there currently exists no practical method to fabricate a self-aligned gate structure with these devices. Therefore, unlike traditional silicon MOSFETs, parasitic capacitance in carbon-based devices is still a concern.
Therefore, techniques for producing carbon-based transistor devices with self-aligned gate structure would be desirable.